High Speed Digital Blocks
Low Power Rail to Rail D Flip-Flop Using Current Mode Logic Structure
KR100682266B1 - Differential output tspc d-type flip flop and frequency divider using it - Google Patents
Figure 1 from Design of low-power high-speed dual-modulus frequency divider with improved MOS current mode logic | Semantic Scholar
Figure 5.21 from Cmos Logic and Current Mode Logic 5.1 Introduction | Semantic Scholar
Schematic timing diagram of the proposed NDR-based CML D flip-flop | Download Scientific Diagram
Figure 1 from A 45 mW RTD/HBT MOBILE D-Flip Flop IC Operating up to 32 Gb/s | Semantic Scholar
![PDF] New CML latch structure for high speed prescaler design | Semantic Scholar](https://d3i71xaburhd42.cloudfront.net/93868f9ab79d1ff6f718775e3548ec22466130cd/2-Figure2-1.png "PDF] New CML latch structure for high speed prescaler design | Semantic Scholar")
PDF] New CML latch structure for high speed prescaler design | Semantic Scholar
MIPI homepage CMOS prescaler basics
Figure 4 from Low power inductor-less CML latch and frequency divider for full-rate 20 Gbps in 28-nm CMOS | Semantic Scholar
adding reset function to D Flip FLOP | Forum for Electronics
Analysis and Design of High-Speed CMOS Frequency Dividers
Performance evaluation of the low-voltage CML D-latch topology - ScienceDirect
A Dynamic Current Mode D-Flipflop for High Speed Application | Semantic Scholar
High speed CML latch using active inductor in 0.18μm CMOS technology | Semantic Scholar
Electronics | Free Full-Text | A Power Efficient Frequency Divider With 55 GHz Self-Oscillating Frequency in SiGe BiCMOS
Low Power Rail to Rail D Flip-Flop Using Current Mode Logic Structure
adding reset function to D Flip FLOP | Forum for Electronics
CML based DFF combined with NAND function used in 4/5 prescaler block | Download Scientific Diagram
An active inductor employed CML latch for high speed integrated circuits | SpringerLink
PPT - Advantages of Using CMOS PowerPoint Presentation, free download - ID:3409185
Help me calculate the device size of CML/SCL latch design and simulate the gain of it | Forum for Electronics
Schematic of standard CML master-slave D-flip flop. | Download Scientific Diagram
Circuit configuration of the RTD/HBT MOBILE-based NRZ D-flip flop. | Download Scientific Diagram
Schematic of standard CML master-slave D-flip flop. | Download Scientific Diagram
An improved current mode logic latch for high‐speed applications - Kumawat - 2020 - International Journal of Communication Systems - Wiley Online Library
Figure 16.23 from Direct-coupled Fet Logic (dcfl) @bullet Source-coupled Fet Logic (scfl) @bullet Advanced Mesfet/hemt Design Examples Iii-v Hbt for Circuit Designers @bullet Current-mode Logic @bullet Emitter-coupled Logic @bullet Ecl/cml Logic Examples @
